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| Microcomputer Components 8-bit CMOS Microcontroller C513AO fin eo n. co m / Data Sheet 02.00 ht tp :// w w w .in DS 1 C513AO Data Sheet Revision History : Previous Releases: Current Version: 02.00 (Original Version) For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com Enhanced Hooks TechnologyTM is a trademark and patent of Metalink Corporation licensed to Infineon Technologies. Edition 02.00 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen (c) Infineon Technologies AG 2000. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 8-Bit CMOS Microcontroller C513AO Advance Information * Full upward compatibility with standard 8051 microcontroller * Up to 16 MHz external operating frequency - 750 ns instruction cycle at 16 MHz operation * On-chip program memory - C513AO-2R: 16 Kbytes ROM (with optional ROM protection) - C513AO-2E: 16 Kbytes OTP - C513AO-L: version without on-chip program memory (ROMless) * Up to 64K byte external data memory * 256 x 8 RAM * 256 x 8 XRAM * Four 8-bit digital I/O ports * Three 16-bit timers/counters (Timer 2 with Up/Down and 16-bit auto-reload features) * Full duplex serial interface (USART) * Synchronous Serial Channel (SSC) * Seven interrupt sources with two priority levels * On-chip emulation support logic (Enhanced Hooks Emulation TechnologyTM) (further features are on next page) On-Chip Emulation Support Module Oscillator Watchdog XRAM 256 x 8 XRAM 256 x 8 Port 0 I/O Timer 2 T0 C500 Core 8-Bit USART Port 1 I/O SSC Interface T1 Port 2 I/O Watchdog Timer ROM/OTP 16 K x 8 Port 3 I/O MCB04006 Figure 1 C513AO Functional Units Data Sheet 1 02.00 C513AO Features (continued): Programmable 15-bit Watchdog Timer Oscillator Watchdog Fast Power On Reset Power Saving Modes - Slow-down mode - Idle mode - Software power-down mode with optional wake up capability through pin P3.2/INT0 * Available in P-DIP40-2, P-LCC-44-1 and P-MQFP-44-2 packages * Fully pin-compatible with C501, C504, C505C, C505CA and C511/C513-devices. TA: 0 to 70 C * Temperature ranges: SAB-C513AO TA: - 40 to 85 C SAF-C513AO Ordering Information The ordering code for Siemens microcontrollers provides an exact reference to the required product. This ordering code identifies: * the derivative itself, i.e. its function set * the specified temperature range * the package and the type of delivery For the available ordering codes for the C513AO please refer to the "Product Information Microcontrollers", which summarizes all available microcontroller variants. * * * * Note: The ordering codes for the Mask-ROM versions are defined for each product after the verification of the respective ROM code. Data Sheet 2 02.00 C513AO VDD VSS Port 0 8-Bit Digital I/O XTAL1 XTAL2 RESET EA ALE PSEN Port 3 8-Bit Digital I/O Port 1 8-Bit Digital I/O C513AO Port 2 8-Bit Digital I/O MCL04007 Figure 2 Logic Symbol Data Sheet 3 02.00 C513AO P1.0/T2 P1.1/T2EX P1.2/SCLK P1.3/SRI P1.4/STO P1.5/SLS P1.6 P1.7 RESET P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 MCP04008 C513AO 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 VSS Figure 3 P-DIP-40-2 Package Pin Configuration (top view) Data Sheet 4 02.00 C513AO P2.4/A12 P2.3/A11 P2.2/A10 P2.0/A8 28 27 26 25 24 23 22 21 20 19 18 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE N.C. EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 17 16 15 14 13 P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TxD N.C. P3.0/RxD RESET P1.7 P1.6 P1.5/SLS C513AO P3.7/RD P3.6/WR 12 11 10 9 8 7 P2.1/A9 XTAL1 P1.1/T2EX VDD VSS P1.0/T2 XTAL2 P1.2/SCLK VDD VSS P1.3/SRI P1.4/STO P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 MCP04009 Figure 4 P-LCC-44-1 Package Pin Configuration (top view) Data Sheet 5 02.00 C513AO P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA N.C. ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 33 32 31 30 29 28 27 26 25 24 23 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 VDD VSS P1.0/T2 P1.1/T2EX P1.2/SCLK P1.3/SRI P1.4/STO P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 C513AO 17 16 15 14 13 12 VDD VSS XTAL1 XTAL2 P3.7/RD P3.6/WR P1.5/SLS P1.6 P1.7 RESET P3.0/RxD N.C. P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 MCP04010 Figure 5 P-MQFP-44-2 Package Pin Configuration (top view) Data Sheet 6 02.00 C513AO Table 1 Pin Definitions and Functions Symbol Pin Number P- DIP P-LCC- P-MQFP-40 44 44 P1.7P1.0 8-1 9-2 3-1, 44-40 I/O Function *) I/O Port 1 Port 1 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 1 pins that have "1s" written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, Port 1 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up transistors. The output latch corresponding to a secondary function must be programmed to 1 for that function to operate. For the outputs of the Synchronous Serial Channel (SSC), SCLK and STO, special circuitry is implemented providing true push-pull capability. The STO output, in addition, will have true tristate capability. When used for SSC inputs, the pull-up transistors will be switched off and the inputs float (high ohm inputs). The secondary functions are assigned to the pins of Port 1 as follows: 1 2 3 4 5 6 *) I = Input O = Output 2 3 4 5 6 7 40 41 42 43 44 1 P1.0 / T2 P1.1 / T2EX P1.2 / SCLK P1.3 / SRI P1.4 / STO P1.5 / SLS Input to Counter 2 Capture/reload trigger of Timer 2 Up-Down count SSC Master Clock Output SSC Slave Clock Input SSC Receive Input SSC Transmit Output Slave Select Input Data Sheet 7 02.00 C513AO Table 1 Pin Definitions and Functions (cont'd) Symbol Pin Number P- DIP P-LCC- P-MQFP-40 44 44 P3.0P.3.7 10-17 11, 13-19 5, 7-13 I/O Function *) I/O Port 3 Port 3 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 3 pins that have "1"s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, Port 3 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up transistors. The output latch corresponding to a secondary function must be programmed to a "1" for that function to operate (except for TxD and WR). The secondary functions are assigned to the pins of Port 3 as follows: 10 11 5 P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface Transmitter data output (asynch.) or clock output (synch.) of serial interface External Interrupt 0 input / Timer 0 gate control input External Interrupt 1 input / Timer 1 gate control input Timer 0 counter input Timer 1 counter input WR control output; latches the data byte from Port 0 into the external data memory RD control output; enables the external data memory to Port 0 11 13 7 P3.1 / TxD 12 13 14 15 16 14 15 16 17 18 8 9 10 11 12 P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 P3.6 / WR 17 RESET 9 19 10 13 4 I P3.7 / RD RESET A high level on this pin for the duration of two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VDD. *) I = Input O = Output Data Sheet 8 02.00 C513AO Table 1 Pin Definitions and Functions (cont'd) Symbol Pin Number P- DIP P-LCC- P-MQFP-40 44 44 XTAL2 XTAL1 18 19 20 21 14 15 I/O Function *) O I XTAL2 Output of the inverting oscillator amplifier. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. P2.0P2.7 21-28 24-31 18-25 I/O Port 2 Port 2 is a an 8-bit quasi-bidirectional I/O port with internal pull-up arrangement. Port 2 pins that have "1s" written to them are pulled high by the internal pull-up transistors, and in that state can be used as inputs. As inputs, Port 2 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup transistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup transistors when issuing "1"s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), Port 2 issues the contents of the P2 Special Function Register and uses only the internal pull-up transistors. O Program Store Enable This is a control signal that enables output of the external program memory to the bus during external fetch operations. It is activated every three oscillator periods except during external data memory accesses. It remains high during internal program execution. This pin should not be driven during reset operation. PSEN 29 32 26 *) I = Input O = Output Data Sheet 9 02.00 C513AO Table 1 Pin Definitions and Functions (cont'd) Symbol Pin Number P- DIP P-LCC- P-MQFP-40 44 44 ALE 30 33 27 I/O Function *) O Address Latch Enable This output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. When instructions are executed from internal program memory (EA = 1) the ALE generation can be disabled by bit EALE in SFR SYSCON. This pin should not be driven during reset operation. External Access Enable When held at high level, instructions are fetched from the internal program memory when the PC is less than 4000H. When held at low level, the C513AO fetches all instructions from external program memory. This pin should not be driven during reset operation. Note: For the C513AO-L this pin must be tied low. EA 31 35 29 I P0.0P0.7 32-39 43-36 37-30 I/O Port 0 Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have "1s" written to them float, and in that state can be used as high-impendance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application, it uses strong internal pull-up transistors when issuing 1s. External pull-up resistors are required during program verification. - - - Ground (0 V) Power Supply (+ 5 V) No Connection. These pins should not be connected. VSS VDD N.C. *) 20 40 - 22, 1 44, 23 12, 34 16, 39 38, 17 6, 28 I = Input O = Output Data Sheet 10 02.00 C513AO VDD VSS XTAL1 XTAL2 C513AO XRAM 256 byte Oscillator Watchdog RAM 256 byte ROM/OTP 16 K x 8 OSC & Timing RESET CPU ALE PSEN EA Timer 1 Port 1 Port 1 8-Bit Digital I/O Port 2 8-Bit Digital I/O Port 3 8-Bit Digital I/O Timer 0 Port 0 Port 0 8-Bit Digital I/O Timer 2 Port 2 Interrupt Unit Port 3 USART Emulation Support Logic SSC MCB04011 Figure 6 Block Diagram of the C513AO Data Sheet 11 02.00 C513AO CPU The C513AO is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 16-MHz crystal, 58% of the instructions execute in 750 ns. Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 Reset Value: 00H LSB D0H P PSW Bit CY AC F0 RS1 RS0 Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag 0 Register bank Select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH OV F1 P Overflow Flag Used by arithmetic instruction. General Purpose Flag 1 Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. Data Sheet 12 02.00 C513AO Memory Organization The C513AO CPU manipulates operands in the following five address spaces: * Up to 64 Kbytes of program memory (up to 16 KB on-chip program memory for the C513AO-2R/ 2E) * Up to 64 Kbytes of external data memory * 256 bytes of internal data memory * 256 bytes of internal XRAM data memory * One 128-byte special function register area Figure 7 illustrates the memory address spaces of the C513AO. FFFFH Ext. Data Memory Internal FFFFH XRAM (256 byte) FF00 H FEFFH Ext. Indirect Addr. Internal RAM FFH 80H Internal RAM Direct Addr. Special Function Regs. 7FH 00H FFH 80H Ext. Data Memory 4000H Int. (EA = 1) Ext. (EA = 0) 3FFFH 0000H "Data Space" 0000H "Code Space" "Internal Data Space" MCA04012 Figure 7 C513AO Memory Map Data Sheet 13 02.00 C513AO Reset and System Clock The reset input is an active high input. An internal Schmitt-trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (24 oscillator periods) while the oscillator is running. With the oscillator running, the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes low again. Figure 8 shows the possible reset circuitries. VDD + VDD C513AO RESET & C513AO RESET + C513AO RESET a) b) c) MCS03291 Figure 8 Reset Circuitries Data Sheet 14 02.00 C513AO Figure 9 shows the recommended oscillator circiutries for crystal and external clock operation. C XTAL2 3.5-16 MHz C513AO XTAL1 C C = 20 pF 10 pF for crystal operation MCS04014 Figure 9 Recommended Oscillator Circuitry In this application, the on-chip oscillator is used as a crystal-controlled, positive-reactance oscillator (a more detailed schematic is given in Figure 10). lt is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal specifications and capacitances are non-critical. In this circuit, 20 pF can be used as single capacitance at any frequency together with a good quality crystal. A ceramic resonator can be used in place of the crystal in cost-critical applications. If a ceramic resonator is used, the two capacitors normally will have different values, dependent on the oscillator frequency. We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors. Data Sheet 15 02.00 C513AO To internal timing circuitry **) C513AO XTAL2 *) XTAL1 C1 C2 *) Crystal or ceramic resonator **) Resistor is only in the C513AO-2E MCS04015 Figure 10 On-Chip Oscillator Circuitry To drive the C513AO with an external clock source, the external clock signal must be applied to XTAL1, as shown in Figure 11. XTAL2 must be left unconnected. A pull-up resistor is suggested to increase the noise margin, but is optional if VOH of the driving gate corresponds to the VIH2 specification of XTAL1. C513AO N.C. XTAL2 VDD External Clock Signal XTAL1 MCS04016 Figure 11 External Clock Source Data Sheet 16 02.00 C513AO Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. ICE-System interface to emulation hardware SYSCON PCON TCON C500 MCU opt. I/O Ports RESET EA ALE PSEN Port 0 Port 2 Port 3 Port 1 RSYSCON RPCON RTCON Enhanced Hooks Interface Circuit RPORT RPORT 2 0 TEA TALE TPSEN EH-IC Target System Interface MCS03254 Figure 12 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. 1 "Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Infineon Technologies. Data Sheet 17 02.00 C513AO Special Function Registers The registers reside in the special function register area, with the exception of the Program Counter and the four General Purpose Register banks. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. Four special function registers of the C513AO (PCON1, VR0, VR1 & VR2) are located in the mapped special function register area. For accessing the mapped special function register area, bit RMAP in special function register SYSCON must be set. All other special function registers of the C513AO are located in the standard special function register area. Special Function Register SYSCON (Address B1 H) Bit No. MSB 7 B1H - 6 - 5 EALE 4 RMAP 3 - 2 - 1 - Reset Value: XX10XXX0B LSB 0 XMAP SYSCON The functions of the shaded bits are not described in this section. Bit RMAP Function Special function Register MAP bit RMAP = 0: The access to the non-mapped (standard) special function register area is enabled. RMAP = 1: The access to the mapped special function register area is enabled. Reserved bits for future use. Read by CPU returns undefined values. - If bit RMAP is set, mapped special function registers can be accessed. This bit is not cleared by hardware automatically. The forty Special Function Registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C513AO are listed in Table 2 and Table 3. In Table 2, they are organized in groups which refer to the functional blocks of the C513AO. Table 3 illustrates the contents of the SFRs in numeric order of their addresses. Data Sheet 18 02.00 C513AO Table 2 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL PSW SP SYSCON2) Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer System Control Register Version Register 0 Version Register 16) Version Register 27) Interrupt Enable Register Interrupt Priority Register Port 0 Port 1 Port 2 Port 3 Power Control Register Serial Channel Buffer Register Serial Channel Control Register SSC Control Register SSC Transmit Register SSC Receive Register SSC Flag Register SSC Interrupt Enable Register SSC Mode Test Register Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Address Contents after Reset E0H1) F0H1) 83H 82H D0H1) 81H B1H FCH FDH FEH A8H1) B8H1) 80H1) 90H1) A0H1) B0H1) 87H 99H 98H1) E8H1) E9H EAH F8H1) F9H EBH 88H1) 8CH 8DH 8AH 8BH 89H 00H 00H 00H 00H 00H 07H XX10XXX0B3) C5H - - 00H X0000000B3) FFH FFH FFH FFH 000X0000B XXH3) 00H 07H XXH3) XXH3) XXXXXX00B3) XXXXXX00B3) 00H 00H 00H 00H 00H 00H 00H VR04) 5) VR14) 5) VR24) 5) Interrupt System Ports IE IP P0 P1 P2 P3 PCON2) SBUF SCON SSCCON STB SRB SCF SCIEN SSCMOD8) TCON TH0 TH1 TL0 TL1 TMOD Serial Channel (USART) SSC Interface Timer 0/ Timer 1 Bit-addressable special function registers This special function register is listed repeatedly since some bits of it also belong to other functional blocks. "X" means that the value is undefined and the location is reserved This SFR is a mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. This SFR is read-only. C513AO-L/2R: 13H C513AO-2E: 83H 7) This SFR varies with the step of the microcontroller: for example, 01H for the first step 8) This register is only used for test purposes and must not be written during normal operation. Unpredictable results may occur upon a write operation. 1) 2) 3) 4) 5) 6) Data Sheet 19 02.00 C513AO Table 2 Special Function Registers - Functional Blocks (cont'd) Block Timer 2 Symbol T2CON T2MOD RC2H RC2L TH2 TL2 WDTREL Name Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload/Capture Register, High Byte Timer 2 Reload/Capture Register, Low Byte Timer 2 High Byte Timer 2 Low Byte Watchdog Timer Control Register Watchdog Timer Reload Register Power Control Register Power Control Register 1 Address Contents after Reset C8H1) C9H CBH CAH CDH CCH C0H1) 86H 87H 88H 00H XXXXXXX0B3) 00H 00H 00H 00H XXXX0000B3) 00H 000X0000B3) 0XXXXXXXB3) Watchdog WDCON Power Save Mode 1) 2) 3) 4) 5) 6) PCON2) PCON14) Bit-addressable special function registers This special function register is listed repeatedly since some bits of it also belong to other functional blocks. "X" means that the value is undefined and the location is reserved This SFR is a mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. This SFR is read-only. C513AO-L/2R: 13H C513AO-2E: 83H 7) This SFR varies with the step of the microcontroller: for example, 01H for the first step 8) This register is only used for test purposes and must not be written during normal operation. Unpredictable results may occur upon a write operation. Data Sheet 20 02.00 C513AO Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses Addr. Register Content Bit 7 after Reset1) FFH 07H 00H 00H .7 .7 .7 .7 WDT PSEL SMOD TF1 EWPD GATE .7 .7 .7 .7 - SM0 .7 .7 EA RD - - - Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H2) 81H 82H 83H 86H 87H P0 SP DPL DPH .6 .6 .6 .6 .6 - TR1 - C/T .6 .6 .6 .6 - SM1 .6 .6 WR - .5 .5 .5 .5 .5 - TF0 - M1 .5 .5 .5 .5 .SLS SM2 .5 .5 T1 .4 .4 .4 .4 .4 SD TR0 - M0 .4 .4 .4 .4 STO REN .4 .4 ES T0 .3 .3 .3 .3 .3 GF1 IE1 - GATE .3 .3 .3 .3 SRI TB8 .3 .3 ET1 INT1 - PT1 .2 .2 .2 .2 .2 GF0 IT1 - C/T .2 .2 .2 .2 RB8 .2 .2 EX1 INT0 - PX1 .1 .1 .1 .1 .1 PDE IE0 - M1 .1 .1 .1 .1 TI .1 .1 ET0 TxD - PT0 .0 .0 .0 .0 .0 IDLE IT0 - M0 .0 .0 .0 .0 T2 RI .0 .0 EX0 RxD XMAP PX0 SWDT WDTREL 00H PCON 0XX00000B 00H 0XX0XXXXB 00H 00H 00H 00H 00H FFH 00H XXH FFH 00H FFH 88H2) 3) TCON 88H3) 89H 8AH 8BH 8CH 8DH 90H2) 98H2) 99H A0H2) A8H2) B0H2) B1H B8H2) C0H2) 1) 2) 3) 4) 5) 6) PCON1 TMOD TL0 TL1 TH0 TH1 P1 SCON SBUF P2 IE P3 SCLK T2EX ESSC ET2 SYSCON XX10XXX0B IP WDCON EALE RMAP PS - X0000000B XXXX0000B PSSC PT2 - - OWDS WDTS WDT "X" means that the value is undefined and the location is reserved. Bit-addressable special function registers. SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. These are read-only registers. The content of this SFR varies with the actual step of the C513A0: for example, 01H for the first step). This register is only used for test purposes and must not be written during normal operation. Unpredictable results may occur upon a write operation. Data Sheet 21 02.00 C513AO Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont'd) Addr. Register Content Bit 7 after Reset1) 00H XXXXXXX0B 00H 00H 00H 00H 00H 00H XXH XXH 00H XXXXXX00B XXXXXX00B C5H - 7) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C8H2) C9H CAH CBH CCH CDH D0H2) E0H2) E8H2) E9H EAH EBH F0H2) F8H F9H 2) T2CON T2MOD RC2L RC2H TL2 TH2 PSW ACC STB SRB B SCF SCIEN TF2 - .7 .7 .7 .7 CY .7 SCEN .7 .7 .7 - - .7 .7 .7 EXF2 RCLK TCLK - .6 .6 .6 .6 AC .6 TEN .6 .6 .6 - - .6 .6 .6 - .5 .5 .5 .5 F0 .5 .5 .5 .5 - - .5 .5 .5 - .4 .4 .4 .4 RS1 .4 .4 .4 0 .4 - - .4 .4 .4 EXEN2 TR2 - .3 .3 .3 .3 RS0 .3 CPHA .3 .3 0 .3 - - .3 .3 .3 - .2 .2 .2 .2 OV .2 .2 .2 0 .2 - - .2 .2 .2 C/T2 - .1 .1 .1 .1 F1 .1 .1 .1 0 .1 WCOL CP/ RL2 DCEN .0 .0 .0 .0 P .0 BRS0 .0 .0 LSBSM .0 TC SSCCON 07H MSTR CPOL BRS2 BRS1 SSCMOD 00H6) LOOPB TRIO 0 WCEN TCEN .1 .1 .1 .0 .0 .0 FCH3) 4) VR0 FDH 1) 2) 3) 4) 5) 6) 3) 4) VR1 FEH3) 4) VR2 -5) "X" means that the value is undefined and the location is reserved Bit-addressable special function registers SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. These SFRs are read-only registers. The content of this SFR varies with the actual step of the C513A0: for example, 01H for the first step) This register is only used for test purposes and must not be written during normal operation. Unpredictable results may occur upon a write operation. 7) C513AO-L/2R: 13H C513AO-2E: 83H Data Sheet 22 02.00 C513AO Parallel I/O Port The C513AO has four 8-bit I/O ports. Port 0 is an open-drain bidirectional I/O port, while Ports 1, 2, and 3 are quasi-bidirectional I/O ports with internal pull-up resistors. Thus, when configured as inputs, Ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of Port 0 and Port 2 and the input buffers of Port 0 are also used for accessing external memory. In this application, Port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the Port 2 pins continue to emit the P2 SFR contents. In this case, Port 0 is not an open-drain port, but uses a strong internal pull-up Field Effect Transistors (FETs). Port 1 pins used for Synchronous Serial Channel (SSC) outputs are true push-pull outputs. When used as SSC inputs, they float (no pull-up). Data Sheet 23 02.00 C513AO Timer/Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4: Table 4 Timer/Counter 0 and 1 Operating Modes Mode 0 1 2 3 Description 8-bit timer/counter with a divide-by-32 prescaler 16-bit timer/counter 8-bit timer/counter with 8-bit autoreload Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer 1 stops 0 1 1 1 TMOD M1 M0 0 1 0 1 Internal Input Clock External (max.) fOSC/(12 x 32) fOSC/(24 x 32) fOSC/12 fOSC/24 In the "timer" function (C/T = `0') the register is incremented every machine cycle. Since a machine cycle consists of twelve oscillator periods, the count rate is 1/12th of the oscillator frequency. In "counter" function, the register is incremented in response to a 1-to-0 transition (falling edge) at its corresponding external input pin, T0 or T1 (alternate functions of P3.4 and P3.5, respectively). Since it takes two machine cycles to detect a falling edge; therefore, the maximum count rate is 1/ 24th of the oscillator frequency. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 13 illustrates the input clock logic. f OSC / 12 f OSC/12 C/T TMOD 0 /12 P3.4/T0 P3.5/T1 max f OSC/24 TR 0/1 TCON Gate TMOD P3.2/INT0 P3.3/INT1 =1 _ <1 Timer 0/1 Input Clock 1 Control & MCS01768 Figure 13 Timer/Counter 0 and 1 Input Clock Logic Data Sheet 24 02.00 C513AO Timer/Counter 2 with Compare/Capture/Reload Timer 2 is a 16-bit timer/counter with an up/down count feature. It has three operating modes: * 16-bit auto-reload mode (up or down counting) * 16-bit capture mode * Baudrate generator Table 5 Timer / Counter 2 Operating Modes T2CON Mode RCLK CP/ TR2 RL2 or TCLK 0 0 0 0 16-bit Capture 0 0 0 0 0 1 1 1 1 1 1 T2MOD T2CON P1.1/ Remarks T2EX DCEN EXEN2 Input Clock Internal External (P1.0/ T2) 16-bit Autoreload 0 0 1 1 X 0 1 X X 0 X 0 1 X reload upon overflow fOSC/12 reload trigger (falling edge) down counting up counting 16-bit Timer/ Counter (only up-counting) capture TH2, TL2 RC2H, RC2L no overflow interrupt request (TF2) extra external interrupt ("Timer 2") Timer 2 stops max fOSC/24 0 1 1 X 1 fOSC/12 max fOSC/24 Baudrate 1 Generator 1 X 1 X 0 X X 1 X 1 fOSC/12 max fOSC/24 off X X 0 X X X - - Note: denotes a falling edge Data Sheet 25 02.00 C513AO Serial Interface (USART) The serial port is a full duplex port capable of simultaneous transmit and receive functions. It is also receive-buffered; it can commence reception of a second byte before a previously-received byte has been read from the receive register. The serial port can operate in 4 modes (one synchronous and three asynchronous) as illustrated in Table 6. Table 6 USART Operating Modes Mode 0 SCON SM0 0 SM1 0 Shift register mode Serial data enters and exits through RxD. TxD outputs the shift clock. 8-bit data are transmitted/received (LSB first) at a fixed baudrate of 1/12th of the oscillator frequency. 8-bit USART, variable baudrate 10 bits are transmitted (through TxD) or received (at RxD). 9-bit USART, fixed baudrate 11 bits are transmitted (through TxD) or received (at RxD). 9-bit USART, variable baudrate Similar to mode 2, except for the variable baudrate. Description 1 2 3 0 1 1 1 0 1 For clarification, some terms regarding the difference between "baudrate clock" and "baudrate" should be mentioned. The serial interface requires a clock rate which is 16 times the baudrate for internal synchronization. Therefore, the baudrate generators must provide a "baudrate clock" to the serial interface which divides it by 16, thereby resulting in the actual "baudrate". The baudrates in Mode 1 and 3 are determined by the timer overflow rate. These baudrates can be determined by Timer 1 or by Timer 2 or both (one for transmit, the other for receive). Data Sheet 26 02.00 C513AO Timer 1 Overflow fOSC /2 /6 Mode 1 Mode 3 Mode 2 Mode 0 SCON.7/ SCON.6 (SM0/ SM1) /2 PCON.7 (SMOD) 0 1 Baudrate Clock Only one mode can be selected Note: The switch configuration shows the reset state MCS04017 Figure 14 Block Diagram of Baudrate Generation for the Serial Interface Table 7 lists the values/formulas for the baudrate calculation of the serial interface with its dependencies on the control bits SMOD (in SFR PCON), TCLK and RCLK (both in SFR T2CON). Table 7 Serial Interface - Baudrate Dependencies Serial Interface Operating Modes Mode 0 (Shift Register) Mode 1 (8-bit UART) Mode 3 (9-bit UART) Control Bits SMOD - X - Mode 2 (9-bit UART) 0 1 TCLK/RCLK - 0 1 - - Baudrate Calculation fOSC/12 Determined by timer 1 overflow rate: (2SMOD x timer 1 overflow rate)/32 Determined by timer 2 overflow rate: Timer 2 overflow rate/16 fOSC/64 fOSC/32 Data Sheet 27 02.00 C513AO SSC Interface The Synchronous Serial Channel (SSC) interface is compatible to the popular SPI serial bus interface. It can be used for simple I/O expansion via shift registers, for connection with a variety of peripheral components (such as A/D converters, EEPROMs etc.), or interconnection of several microcontrollers in a master/slave structure. The SSC unit supports full-duplex or half-duplex operation and can run in Master Mode or Slave Mode. Figure 15 shows the block diagram of the SSC. f OSC Clock Divider STB Clock Selection Shift Register SRB Receive Buffer Register Interrupt SCIEN Int. Enable Reg. SSCCON Control Register Control Logic SCF Status Register P1.2/SCLK P1.3/SRI Pin Control Logic P1.4/STO P1.5/SLS Internal Bus MCB02735 Figure 15 SSC Block Diagram Interrupt System The C513AO provides seven interrupt sources with two priority levels. Five of the interrupts can be generated by the on-chip peripherals (Timer 0, Timer 1, Timer 2, USART, and SSC) and three of the interrupts may be triggered externally (P1.1/T2EX, P3.2/INT0, P3.3/INT1). A non-maskable eighth interrupt is reserved for external wake-up from power-down mode. Figure 16 gives a general overview of the interrupt sources and illustrates the request and the control flags. Table 8 lists the vector addresses of each interrupt source. Data Sheet 28 02.00 C513AO Figure 16 Interrupt Request Sources Data Sheet 29 02.00 C513AO Table 8 Interrupt Vector Addresses Interrupt Source External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt USART serial port interrupt Timer 2 interrupt Synchronous Serial Channel interrupt (SSC) Wake-up from power-down mode Request Flags IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 WCOL+TC - Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0043H 007BH If two interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level there is a second priority structure determined by the polling sequence as shown in Table 9. Table 9 Interrupt Source Structure Interrupt Source External Interrupt 0 Synchronous Serial Channel Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt Universal Serial Channel Timer 2 Interrupt IE0 WCOL OR TC TFO IE1 TF1 RI OR TI TF2 OR EXF2 Priority High Low A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. Data Sheet 30 02.00 C513AO Fail Save Mechanisms The C513AO offers enhanced fail-safe mechanisms which allow automatic recovery from a software upset or a hardware failure: * A programmable Watchdog Timer (WDT) has variable time-out period from 512 s up to approx. 1.1 sec. at 12 MHz * An Oscillator Watchdog (OWD) monitors the on-chip oscillator and forces the microcontroller into reset state if the on-chip oscillator fails. It also provides the clock for a fast internal reset after power-on. The Watchdog Timer in the C513AO is a 15-bit timer which is incremented by a count rate of either fCYCLE/2 or fCYCLE/32 (fCYCLE = fOSC/12). That is, the machine clock is divided by a fixed divide-by-two prescaler and an optional divide-by-16 prescaler arranged in series. For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 17 shows the block diagram of the watchdog timer unit. Figure 17 Block Diagram of the Watchdog Timer The Watchdog Timer can be started by software (bit SWDT in SFR WDCON); but, it cannot be stopped during active mode of the device. If the software fails to clear the Watchdog Timer, an internal reset will be initiated. The reset cause can be examined by software (status flag WDTS in WDCON is set). A refresh of the Watchdog Timer is done by setting bits WDT (SFR WDCON) and SWDT consecutively. This double instruction sequence has been implemented to increase system security. During a refresh, the content of the SFR WDTREL is transferred to SFR WDTH, i.e. the upper 7-bit of the watchdog timer. It must be noted, however, that the watchdog timer is stopped during the idle mode and power down mode of the processor. Data Sheet 31 02.00 C513AO Oscillator Watchdog The Oscillator Watchdog (OWD) unit is used for three functions: * Monitoring the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency. If the frequency is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset. If the failure condition disappears (that is, if the on-chip oscillator has a higher frequency than the RC oscillator), the device executes a final reset phase of typically 1 ms to allow the oscillator to stabilize. Then, the oscillator watchdog reset is released and the device resumes program execution. * Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for reset before the on-chip oscillator has started. The oscillator watchdog unit reset works identically to the monitoring function. * Control of external wake-up from software power-down mode When power-down mode is terminated by a low level at the INT0 pin, the oscillator watchdog unit ensures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In power-down mode, the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is terminated. When the on-chip oscillator has a frequency higher than the RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms to allow the on-chip oscillator to stabilize. Note: The Oscillator Watchdog unit is always enabled. Figure 18 shows the block diagram of the Oscillator Watchdog unit. Data Sheet 32 02.00 C513AO Figure 18 Block Diagram of the Oscillator Watchdog Data Sheet 33 02.00 C513AO Power Saving Modes The C513AO provides three basic power-saving modes: Idle Mode, Slow-down Mode, and Powerdown Mode. * Idle mode The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to function. Idle mode is entered by software and can be left by an interrupt or reset. * Slow down mode The controller keeps up the full operating functionality, but its normal clock frequency is internally divided by 32. This slows down all parts of the controller, the CPU and all peripherals, to 1/32nd of their normal operating frequency and also reduces power consumption. * Power down mode The operation of the C513AO is completely stopped and the oscillator is turned off. This mode is used to save the contents of the internal RAM with a very low standby current. This power down mode is entered by software and can be left by reset or a short low pulse at pin P3.2/INT0. In the power down mode of operation, VDD can be reduced to minimize power consumption. It must be ensured, however, that VDD is not reduced before the power down mode is invoked, and that VDD is restored to its normal operating level, before the power down mode is terminated. Table 10 gives a general overview of the entry and exit procedures of the power saving modes. Table 10 Power Saving Modes Overview Mode Idle mode Entering Example ORL PCON, #01H Leaving by Remarks Occurrence of an any CPU clock is stopped; enabled interrupt CPU maintains their data; peripheral units are active (if Hardware reset enabled) and provided with clock ANL PCON,#0EFH or Hardware reset Occurrence of any enabled interrupt and the instruction ANL PCON,#0EFH Hardware reset Hardware reset Internal clock rate is reduced to 1/32 of its nominal frequency CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with 1/32 of its nominal frequency Slow Down Mode In normal mode: ORL PCON,#10H With idle mode: ORL PCON,#11H Power Down Mode ORL PCON, #02 H Oscillator is stopped; Short low pulse at pin contents of on-chip RAM and SFRs are maintained; P3.2/INT0 Data Sheet 34 02.00 C513AO Absolute Maximum Ratings Parameter Storage temperature Voltage on VDD pins with respect to ground (VSS) Voltage on any pin with respect to ground (VSS) Input current on any pin during overload condition Symbol min. Limit Values max. 150 6.5 C V V mA mA W - - - - - - - 65 - 0.5 - 0.5 - 10 - - Unit Notes TST VDD VIN - VDD + 0.5 10 |100 mA| t.b.d. Absolute sum of all input currents - during overload condition Power dissipation PDISS Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Operating Conditions Parameter Supply voltage Ground voltage Ambient temperature SAB-C513AO SAF-C513AO CPU clock Symbol min. Limit Values max. 5.5 0 0 - 40 3.5 70 85 16 MHz - V V C - - - 4.25 Unit Notes VDD VSS TA TA fCPU Data Sheet 35 02.00 C513AO Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C513AO and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the C513AO will provide signals with the respective characteristics. SR (System Requirement): The external system must provide signals with the respective characteristics to the C513AO. DC Characteristics (Operating Conditions apply) Parameter Input low voltage Pins except EA, RESET EA pin RESET pin Input high voltage Pins except XTAL1, RESET XTAL1 pin RESET pin Output low voltage Ports 1, 2, 3 (except P1.2, P1.4) Port 0, ALE, PSEN P1.2, P1.4 pull-up transistor resistance Output High Voltage Ports 1, 2, 3 Port 0 in external bus mode, ALE, PSEN P1.2, P1.4 pull-up transistor resistance Logic 0 input current Ports 1, 2, 3 Logical 0-to-1 transition current, Ports 1, 2, 3 Input Leakage Current Port 0, EA P1.2, P1.3, P1.5 as SSC inputs Input high current to RESET for reset Symbol min. Limit Values max. 0.2 VDD - 0.1 V 0.2 VDD - 0.3 V 0.2 VDD + 0.1 V - - - - - - Unit Test Condition VIL VIL1 VIL2 VIH VIH1 VIH2 VOL VOL1 RDSON SR SR SR - 0.5 - 0.5 - 0.5 0.6 VDD 0.7 VDD 0.6 VDD - - - SR SR SR VDD + 0.5 VDD + 0.5 VDD + 0.5 0.45 0.45 120 V V V V V CC CC CC I OL = 1.6 mA1) I OL = 3.2 mA1) VOL = 0.45 V VOH VOH1 RDSON CC CC CC 2.4 0.9 VDD 2.4 0.9 VDD - - - - - 120 V V V V IOH = - 80 A, IOH = - 10 A IOH = - 800 A, IOH = - 80 A2) VOH = 0.9 VDD IIL ITL ILI SR - 10 - 65 - - 70 - 650 1 A A A VIN = 0.45 V V IN = 2 V 0.45 < VIN < VDD SR CC IIH CC 5 100 A 0.6 < VIN < VDD Data Sheet 36 02.00 C513AO DC Characteristics (cont'd) (Operating Conditions apply) Parameter Input low current to XTAL1 Pin capacitance Overload current Notes see next page. Symbol min. Limit Values max. - 20 10 5 - - - Unit Test Condition A pF mA VI N = 0.45 V f C = 1 MHz, IIL2 C IO IOV CC CC T A = 25 C 8) 9) SR Power Supply Current Parameter Active mode Symbol Limit Values Unit Test Condition typ.10) max. C513AO-2E 12 MHz IDD 16 MHz IDD C513AO-2R 12 MHz IDD 16 MHz IDD Idle mode C513AO-2E 12 MHz IDD 16 MHz IDD C513AO-2R 12 MHz IDD 16 MHz IDD Active mode with slow-down enabled C513AO-2E 12 MHz IDD 16 MHz IDD C513AO-2R 12 MHz IDD 16 MHz IDD Idle mode with slow-down enabled C513AO-2E 12 MHz IDD 16 MHz IDD C513AO-2R 12 MHz IDD 16 MHz IDD Power-down mode C513AO-2E C513AO-2R 10.3 13.1 6.9 8.5 5.7 6.8 4.1 4.8 4.5 5.1 3.3 3.6 3.7 4.0 2.6 2.8 8.8 1.28 13.0 16.6 9.0 10.9 7.2 8.7 5.5 6.0 5.7 6.5 4.1 4.5 4.7 5.1 3.3 3.5 50 20 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A 4) 4) 5) 5) 6) 6) 7) 7) IPD IPD VDD = 2 ... 5.5 V 3) VDD = 2 ... 5.5 V 3) Data Sheet 37 02.00 C513AO Notes: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt-trigger, or use an address latch with a Schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the address lines are stabilizing. 3) IPD (power-down mode) is measured under following conditions: EA = Port0 = VDD; RESET = VSS; XTAL2 = N.C.; XTAL1 = VSS; all other pins are disconnected. IDD would be slightly higher if a crystal oscillator is used (appr. 1 mA). 4) IDD (active mode) is measured with: XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL1 = N.C.; EA = PE/SWD = Port 0 = Port 6 = VDD; HWPD = VDD; RESET = VDD; all other pins are disconnected. IDD would be slightly higher if a crystal oscillator is used (appr. 1 mA). 5) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS; Port0 = VDD; all other pins are disconnected. 6) IDD (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS; Port0 = VDD; all other pins are disconnected. 7) IDD (idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS; Port0 = VDD; all other pins are disconnected. 8) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VDD and VSS must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA. 9) Not 100% tested, guaranteed by design characterization. 10)The typical IDD values are periodically measured at TA = + 25 C and VDD = 5 V but not 100% tested. Data Sheet 38 02.00 C513AO C513AO-2E 17.5 mA MCD04314 DD 15 12.5 DD max DD typ Acti ve M ode Activ 10 7.5 5 2.5 Active + Slow Down Mode 0 2 4 6 8 10 e Mo de e Idle Mod ode Idle M Idle + Slow Down Mode 12 14 MHz f OSC 16 C513AO-2R 14 mA MCD04315 DD 12 10 8 6 4 2 DD max DD typ e Mo de Activ Active Mode Idle Mode Idle Mode Active + Slow Down Mode 0 2 4 6 8 10 Idle + Slow Down Mode 12 14 MHz f OSC 16 Figure 19 IDD Diagram Data Sheet 39 02.00 C513AO Power Supply Current Calculation Formula Parameter Active mode C513-2E C513-2R Idle mode C513-2E C513-2R Active mode with slow-down enabled C513-2E C513-2R Idle mode with slow-down enabled C513-2E C513-2R Symbol Formula 0.70 x fOSC + 1.8 0.91 x fOSC + 2.0 0.40 x fOSC + 2.1 0.48 x fOSC + 3.2 0.29 x fOSC + 2.2 0.36 x fOSC + 2.9 0.18 x fOSC + 1.9 0.13 x fOSC + 3.9 0.15 x fOSC + 2.6 0.20 x fOSC + 2.9 0.08 x fOSC + 2.4 0.10 x fOSC + 2.9 0.09 x fOSC + 2.5 0.12 x fOSC + 3.2 0.05 x fOSC + 2.0 0.05 x fOSC + 2.7 IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max Note: fosc is the oscillator frequency in MHz. IDD values are given in mA. Data Sheet 40 02.00 C513AO AC Characteristics (16 MHz) (Operating Conditions apply) (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Parameter Symbol 16 MHz Clock min. Program Memory Characteristics ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN *) Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 16 MHz min. max. Unit max. tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) t tAVIV tAZPL CC CC CC SR CC CC SR SR SR 85 33 28 - 38 153 - 0 - 48 - 0 - - - 150 - - 88 - 43 - 198 - 2 tCLCL - 40 - - - 4 tCLCL - 100 - - 3 tCLCL - 100 - ns ns ns ns ns ns ns ns ns ns ns ns tCLCL - 30 tCLCL - 35 - tCLCL - 25 3 tCLCL - 35 - 0 - tCLCL - 20 - 5 tCLCL - 115 - *) PXAV CC SR CC tCLCL - 8 - 0 Interfacing the C513AO to devices with float times up to 55 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Data Sheet 41 02.00 C513AO AC Characteristics (16 MHz, cont'd) (Operating Conditions apply) (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Parameter Symbol 16 MHz Clock min. External Data Memory Characteristics RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 16 MHz min. max. Unit tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ CC CC CC SR SR SR SR SR CC CC CC CC CC CC CC 275 275 90 - 0 - - - 138 120 23 13 288 13 - - - - 148 - 55 350 398 238 - 103 - - - 0 6 tCLCL - 100 6 tCLCL - 100 2 tCLCL - 35 - 0 - - - 3 tCLCL - 50 4 tCLCL - 130 - - - 5 tCLCL - 165 - 2 tCLCL - 70 8 tCLCL - 150 9 tCLCL - 165 3 tCLCL + 50 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCLCL - 40 tCLCL - 50 7 tCLCL - 150 tCLCL + 40 - - - 0 tCLCL - 50 - Data Sheet 42 02.00 C513AO Synchronous Serial Channel (SSC) Interface Characteristics Parameter Symbol min. Clock Cycle Time: Master Mode Slave Mode Clock High Time Clock Low Time Data Output Delay Data Output Hold Data Input Setup Data Input Hold TC Bit Set Delay Limit Values 16 MHz Clock max. - - - - 100 - - - 16 tCLCL ns ns ns ns ns ns ns ns ns Unit tSCLK tSCLK tSCH tSCL tD tHO tS tHI tDTC CC SR 1) CC/SR 1) CC/SR CC CC SR SR CC 500 450 200 200 - 0 80 80 - 1) This parameter is `CC' in Master Mode, and `SR' in Slave Mode. External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 3.5 MHz to 16 MHz min. Oscillator period High time Low time Rise time Fall time max. 285 ns ns ns ns ns Unit tCLCL tCHCX tCLCX tCLCH tCHCL SR SR SR SR SR 62.5 15 15 - - tCLCL - tCLCX tCLCL - tCHCX 15 15 Data Sheet 43 02.00 C513AO t LHLL ALE t AVLL t LLPL t LLIV t PLIV PSEN t PLPH t AZPL t LLAX t PXAV t PXIZ t PXIX Port 0 A0 - A7 Instr.IN A0 - A7 t AVIV Port 2 A8 - A15 A8 - A15 MCT00096 Figure 20 Program Memory Read Cycle Data Sheet 44 02.00 C513AO t WHLH ALE PSEN t LLDV t LLWL RD t RLRH t RLDV t AVLL t LLAX2 t RLAZ Port 0 A0 - A7 from Ri or DPL Data IN t RHDZ t RHDX A0 - A7 from PCL Instr. IN t AVWL t AVDV Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00097 Figure 21 Data Memory Read Cycle Data Sheet 45 02.00 C513AO t WHLH ALE PSEN t LLWL WR t WLWH t QVWX t AVLL t LLAX2 A0 - A7 from Ri or DPL t WHQX t QVWH Data OUT A0 - A7 from PCL Instr.IN Port 0 t AVWL Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00098 Figure 22 Data Memory Write Cycle Data Sheet 46 02.00 C513AO t SCLK t SCL SCLK t SCH tD STO MSB t HD ~ ~ LSB tS SRI t HI MSB ~ ~ ~ ~ ~ ~ LSB ~ ~ t DTC TC ~ ~ MCT02417 Notes: Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is valid for the other cases accordingly. In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the falling edge of SLS (if transmitter is enabled). In the case of master mode and CPHA = 0, the MSB becomes valid after the data has been written into the shift register, i.e. at least one half SCLK clock cycle before the first clock transition. Figure 23 SSC Timing t CLCL VDD- 0.5V 0.7 VDD 0.2 VDD - 0.1 0.45V t CHCL t CLCX t CLCH t CHCX MCT00033 Figure 24 External Clock Drive on XTAL1 Data Sheet 47 02.00 C513AO OTP Memory Characteristics (C513AO-2E only) Programming Mode Timing Characteristics (Operating Conditions apply) Parameter PALE Pulse Width PMSEL Set-up to PALE Rising Edge Address Set-up to PALE, PROG, or PRD Falling Edge Address Hold after PALE, PROG, or PRD Falling Edge Address, Data Set-up to PROG or PRD Address, Data Hold after PROG or PRD PMSEL Set-up to PROG or PRD PMSEL Hold after PROG or PRD PROG Pulse Width PRD Pulse Width Address to Valid Data out PRD to Valid Data out Data Hold after PRD Data float after PRD PROG High between two Consecutive PROG Low Pulses PRD High between two Consecutive PRD Low Pulses XTAL Clock Period Symbol min. Limit Values max. - - - - - - - - - - 75 20 - 20 - - 286 ns - ns ns ns ns ns ns s ns ns ns ns ns s ns ns 35 10 10 10 100 0 10 10 100 100 - - 0 - 1 100 62.5 Unit tPAW tPMS tPAS tPAH tPCS tPCH tPMS tPMH tPWW tPRW tPAD tPRD tPDH tPDF tPWH1 tPWH2 tCLKP Data Sheet 48 02.00 C513AO tPAW PALE tPMS PMSEL1, 0 H, H tPAS Port 2 Port 0 tPAH A0-7 D0-7 A8-13 tPCH PROG tPCS tPWW tPWH MCT04318 Notes: PRD must be high during a programming write cycle Figure 25 Programming Code Byte - Write Cycle Timing Data Sheet 49 02.00 C513AO tPAW PALE tPMS PMSEL1, 0 H, H tPAS Port 2 tPAH A0-7 A8-13 tPAD Port 0 D0-7 tPDH tPRD PRD tPDF tPCH tPCS tPRW tPWH MCT04319 Notes: PROG must be high during a programming read cycle Figure 26 Verify Code Byte - Read Cycle Timing Data Sheet 50 02.00 C513AO PMSEL1, 0 H, L H, L Port 0 D0, D1 D0, D1 tPCS tPMS PROG tPCH tPMH tPDH tPWW tPMS tPRD tPDR tPMH PRD tPRW Notes: PALE should be low during a lock bit read/write cycle MCT04320 Figure 27 Lock Bit Access Timing PMSEL1, 0 Port 2 L, H e.g. FDH tPCH Port 0 D0-7 tPCS tPRD tPMS PRD tPDH tPDF tPMH tPRW Notes: PROG must be high during a programming read cycle MCT04321 Figure 28 Version Registers - Read Timing Data Sheet 51 02.00 C513AO OTP Verification Mode Characteristics Note: ALE pin described below is not the OTP Programming Mode pin PALE Parameter ALE Pulse Width ALE Period Data Valid after ALE Data Stable after ALE P3.5 Set-up to ALE Low Oscillator Frequency Symbol min. Limit Values typ 2 tCLCL 12 tCLCL - - max. - - 4 tCLCL - - 6 ns ns ns ns ns MHz - - - 8 tCLCL - 4 Unit tAWD tACY tDVA tDSA tAS 1/tCLCL tCLCL - tACY tAWD ALE tDSA tDVA Port 0 Data Valid tAS P3.5 MCT04322 Figure 29 OTP Verification Mode Data Sheet 52 02.00 C513AO V DD -0.5 V 0.2 VDD +0.9 Test Points 0.2 VDD -0.1 MCT00039 0.45 V AC Inputs during testing are driven at VDD - 0.5 V for a logic "1" and 0.45 V for a logic "0". Timing measurements are made at VIHmin for a logic "1" and VILmax for a logic "0". Figure 30 AC Testing: Input, Output Waveforms VLoad +0.1 V VLoad VLoad -0.1 V Timing Reference Points VOH -0.1 V VOL +0.1 V MCT00038 For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA. Figure 31 AC Testing: Float Waveforms Data Sheet 53 02.00 C513AO Crystal Oscillator Mode Driving from External Source N.C. C XTAL2 3.5-16 MHz XTAL2 C XTAL1 External Oscillator Signal XTAL1 Crystal Mode: C = 20 pF 10 pF (incl. stray capacitance) MCS04317 Figure 32 Recommended Oscillator Circuits for Crystal Oscillator Data Sheet 54 02.00 C513AO Package Outlines Plastic Package, P-DIP-40-2 (Plastic Dual In-Line Package) 0.5 min 5.1 max 15.24 0.2 3.7 0.3 2.54 40 1.5 max 0.45 +0.1 0.25 40x 0.25 +0.1 14 -0.3 15.24 +1.2 ~ 1.3 ~ 21 1 50.9 -0.5 20 0.25 max Index Marking GPD05055 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Data Sheet 55 Dimensions in mm 02.00 C513AO Plastic Package, P-LCC-44-1 (Plastic Lead Chip Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Data Sheet 56 Dimensions in mm 02.00 GPL05102 C513AO Plastic Package, P-MQFP-44-2 (Plastic Metric Quad Flat Pack) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Data Sheet 57 Dimensions in mm 02.00 GPM05622 |
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